Notice who write this...
Nonetheless, he echoes some of the things that Anand pointed out in his article a couple days ago. This is what I was getting at with this post a while back:
GT300 / Tesla / Fermi Board Fake?
A proper learning vehicle (in ATi's case it was 4770) is needed to understand how to make things yield, to know which ground rules can be pushed and which cannot. Pushing against ground rules is bad for yield, making a huge chip is bad for yield, and not using redundant vias is ****ing terrible for yield. I was talking with a senior engineer about this today, and he said that he first started using redundant vias in his layout in the mid to late '80s. He was absolutely baffled that it is not standard practice.
Regarding the author's comment that TSMC failed badly, I don't agree with that. Clearly their process works, you just have to know how to design for it.
[EDIT]
Didn't finish reading the whole article yet because I need to go to sleep, but I just want to comment on a couple things he said:
1) reworking metal levels doesn't help yield
That's partly true. If their problems are with vias and leaky devices like everyone is saying, then no, it won't help. If they fixed wires that were undersized, then yes it might help, either for timings or end-of-life degradation. Charlie was right that metal level fixes are normally for logic patches, but from his wording I got the impression that he didn't really understand what he was saying.
2) a full relayout is needed to fix the problems
If what has been claimed about their specific issues is true, then yes. If they did in fact build everything to the min size possible and didn't leave any fat, and if they really did use single vias to save space then it is presumable that it is the case, then there is no way to drop redundant vias in without relaying most of the circuits. That is the sad truth.