Memory overclocking and Timings explained
Memory Over clocking and
Memory Timings Explained
So many times you may have heard the statement
“(I can pass memtest86 and Prime95 but fail Orthos after a few minutes)”
Chances are its memory related and not the FSB or voltages that cause early torture tests failures.
The same holds true for hitting the walls that other people seem to scale effortlessly.
Even if your stable while running Orthos 72 hours straight your system crashes and Locks up in games forcing the dreaded Format and reload process.
Or while running folding@home SMP you’re able to complete all WU’s except the highly optimized 2652 even at stock clocks.
This is where memory latency and sub timings come in during your initial burn in process.
Unfortunately there is only one way to test for this failure and that’s crashing your rig.
Let’s begin with a little basic memory theory.
Memory is not just a physical chip inserted into a slot in the motherboard.
It’s a very complex electrical device that consists of communication paths transferring and retrieving bits of data through circuits
This transfer of data through the CPU, Memory controller, and digital logic circuits have to be assigned some sort of orderly destination within a given frame of time and when the data is spent it needs to terminate to start the process all over again.
Within the ram module and the motherboard there are regulation circuits both on the motherboard close to the memory slots and within the PCB of the ram module itself in some DDR2 memory modules.
With this in mind you may or may not be able to increase stability with applied voltage in the memory circuit.
So how can I increase the frequency of the ram without causing data loss or registry errors and without running my voltage up to the point of failure?
The answer again is Memory Latency Timings and sub timings.
We will start with CAS Latency (column address strobe).
Even though this is not the first sequence of events in the timing and command of bits of data it is usually referenced in the quality or overall speed of the module or paired sets of ram modules (CL4…CL5)
These rows and columns consist of capacitors which store electrical charges of information or data that will be accessed, read or retrieved when needed.
“Data is stored in individual memory cells, each uniquely identified by a memory bank, row, and column. To access DRAM, controllers first select a memory bank, then a row (using the row address strobe, RAS), then a column (using the CAS), and finally request to read the data from the physical location of the memory cell. The CAS Latency is the number of clock cycles that elapse from the time the request for data is sent to the actual memory location until the data is transmitted from the module. The data is organized bitwise. It is only assembled into bytes to meet the processor interface. Sometimes this happens on chip, and sometimes on the memory module. It is important to note that for all modern memory, many bits are accessed for each memory read. As an example, when DDR is read, a single read produces 64 bits of data. When discussing latencies, one should keep in mind that when talking about the time between bits, it is referring to the time from the appearance of the first group of bits until the appearance of the next group of bits.”
CAS latency - Wikipedia, the free encyclopedia
A very important aspect of latency timing that is mostly overlooked and misunderstood is that CL timings of 4 clocks cycles is not necessarily faster than a timing of CL5 because in the over clocking world as you increase the frequency the decrease in access time between bits is noticeable.
At 100 MHz at CL2 request may be 10 ns per cycle where at 133 MHz the request may take 7.5 ns per cycle at CL3 and so forth.
This is the part of over clocking that should be addressed for stability issues.
Lower CAS latency is not always faster than higher CAS latency when the frequency is increased in our world of extreme enthusiasts and Gamers.
http://i201.photobucket.com/albums/a...16-23-28-1.png
http://i201.photobucket.com/albums/a...16-15-55-1.png
This is true in most circumstances in the real world but with higher quality ram and cooling you can defy the laws and theory of electronics with a little boost of voltage and tweaking of the sub timings in the memory section of the bios.
The bandwidth increase will change from chipset to chipset and no two motherboards clock the same.
Sometimes the trick to stabilizing you over clock is a simple loosening of the sub timings
Example
This is the settings for my particular Ram DDR2 6400 at 2.2volts
CAS 4
RAS to CAS 4
RAS precharge 3
RAS to active precharge 8
TWR 5
TRFC 30
TWTR 5
TRRD 5
TRTP 5
Although this setting passed all stress tests it failed WU 2652 repeatedly even at stock clocks.
A simple adjustment of the sub timings cleared up the errata and data loss and I regained my over clock settings for 24/7 @ 2.2volts 3.6 GHZ
TRW 9
TRFC 35
TWTR 9
TRRD 9
TRTP 9
For bench marking of course you will enjoy greater bandwidth tightening all latency settings and stabilize you’re over clock with higher voltage and better cooling.
Again this is dependent on the quality of the module and whether or not the Ram has voltage regulation on chip such as Elpeda and Promo.
These IC’c do not respond to increases in voltage but can be clocked higher with latency changes with out sacrificing bandwidth.
1T and 2T clocking is in reference to the address and command bus.
In most applications and dependent on motherboard and module both 1T and 2T support may be available.
2T timing is set by default.
The PDF link below from Micron Technology Inc best explains the address and command bus function
http://download.micron.com/pdf/techn...2/tn_47_01.pdf
Below is a list of Memory modules and the IC's used during manufacturing.
someone went through a lot of work identifying and documenting this usefully golden list.
My hats off to the author :notworthy:
Ramlist moves to i4memory.com
http://forum.xcpus.com/overclocking/...d-part-ii.html
