Intel and Micron: 25nm SSDs in Q4

[billdcat4]

AnandTech: Intel & Micron Announce 25nm NAND Flash Production, SSDs to get Bigger/Cheaper in Q4

Today IMFT is announcing that it has begun sampling 2-bits-per-cell MLC NAND flash manufactured using 25nm transistors. The company believed it had a 6 month head start over the competition in 34nm, and now believes that with 25nm NAND it’s roughly a year ahead of anyone else.

Volume production will happen sometime in Q2, with products shipping before the end of the year. In my last SSD article I mentioned that Intel’s 3rd generation X25-M would be shipping in Q4 at 160GB, 320GB and 600GB. These drives will use IMFT’s new 25nm flash.

The first 25nm product is an 8GB (64Gbit) 2-bits-per-cell MLC NAND flash. A single 8GB die built on IMFT’s 25nm process has a die size of 167mm2. Immersion lithography is apparently necessary to produce these 25nm NAND devices, but the extent is unclear. This is technically Intel’s first device that requires immersion lithography to manufacture.

If IMFT can ramp up production of 25nm NAND flash, 2012 may be the year of the first truly affordable mainstream SSDs.

[billdcat4]

Because of this, I might hold off getting a G2 for my dads next laptop at the end of the summer for the next gen.

$230 for 160gb 25nm? Sign me up!

[SuperFly03]

Good luck with that price Billd

[billdcat4]

Good luck with that price Billd

. At 25nm you basically get twice the capacity at the same die size, which should translate into twice the SSD capacity at the same price as a 34nm drive today.
Obviously supply and demand economics play their roles here. We may not see the sort of aggressive pricing we want to on 25nm X25-M drives if demand remains as high as it has been for the 34nm G2s.

[wuzy]

I'm looking to ramp to the load for some database on my server, but refrained from doing so until I can find enough IOps that's more affordable. At current price $/IOps wise Intel SSD are almost 8x better than a pack of used 4x15k SAS drives, while in reversal it's 2x better in $/GB.

[brentpresley]

...while in reversal it's 2x better in $/GB.

Not when you factor in power over the life of those drives.

[randomizer]

I wonder how they're dealing with the significant reduction in lifespan this will cause (as with 34nm NAND compared to 50nm).

[billdcat4]

I wonder how they're dealing with the significant reduction in lifespan this will cause (as with 34nm NAND compared to 50nm).

wha?

[randomizer]

Process shrinks reduce the lifespan of each cell in a block, and since one unusable cell means the block can't be used any more, the whole block's lifespan is affected.

For SLC there are threshold voltages for programmed and erased states 0 and 1 respectively with a reference voltage in between. These voltages determine whether a current can flow (erased state) through the transistor or is blocked (programmed state). Each cell has a +/- deviation from the ideal threshold voltages since they're not perfect. For MLC there are 4 threshold voltages, one for each state (00,01,10 and 11), and therefore each cell has a narrower tolerance for voltages that deviate from the specified threshold voltage for that state. As a cell ages, the floating gate loses its ability to trap electrons and maintain the correct threshold voltage. If a cell can no longer trap enough electrons in the FG to block current flow (or correctly limit the current flow for the 01 and 10 MLC states,) it can not be programmed, and the whole block must be marked bad.

The Process shrinks reduce the total number of electrons that can be trapped in the floating gate, and this further narrows the differences in voltage thresholds between a programmed and erased state in SLC, and between different programmed states for MLC. This means it will "fail" earlier. If MLC went to 3 bits per cell, you'd have even narrower tolerances.

Of course, there is also the opposite problem where the "gap" between the substrate and the FG traps electrons, requiring longer erase cycles and eventually preventing the cell from erasing correctly. This also means the block must be marked bad.

[huddy]

Cool to see. I don't want to wait that long, but I probably will, seeing as how I would like to put 120 or 160GB SSD's in both my laptop and desktop... doing so is quite a pretty penny at the current prices.

[billdcat4]

DailyTech - IMFT's 25nm NAND Flash Will Cut Production Costs in Half, Spur New SSDs

The most advanced semiconductor process yet

Intel currently has the best selling solid state drive on the market, while Micron has just started shipping the fastest SSD available using the 6Gbps SATA interface. The secret weapon of the two companies is IM Flash Technologies, their joint venture that produces cutting edge 34nm NAND flash memory. Not only does it ensure a steady supply in turbulent times, but it combines the technology and manufacturing prowess of two tech titans together to combat NAND market leaders Samsung and Toshiba.

“Through our continued investment in IMFT, we’re delivering leadership technology and manufacturing that enables the most cost-effective and reliable NAND memory,” said Tom Rampone, Vice President and General Manager of Intel's NAND Solutions Group.

DailyTech saw some 22nm shuttle test wafers at last year's Intel Developer Forum. The world's largest semiconductor company expects to introduce the new process at the end of next year for its Ivy Bridge CPUs, but needs to do a lot of development work first. One of the best ways to do that is to develop a less advanced intermediary step, and the partnership with IMFT allows them to do just that.

IMFT has developed a new 64Gb (8GB) NAND flash memory chip in a compact 167mm2, doubling the density of its 32Gb chips built on the 34nm process. The company will thus be able to produce twice as much capacity for roughly the same cost at its fab in Lehi, Utah, which is currently producing 34nm flash. Development of the 25nm process (codenamed L74) using 300mm wafers was spearheaded by Micron's Fab 4 in Boise, Idaho.

Frequent readers may recall that IMFT announced its 34nm process in November of 2008, but had problems ramping into mass production until the summer of last year. This was primarily due to difficulties in skipping the 43nm node and going directly to 34nm from 50nm. However, we spoke with Dave Baglee and Rod Morgan, IMFT's Co-executive Officers, who assured us that the ramp has been progressing very smoothly.

Yields are much better than the 34nm during the same timeframe, and write speeds will be similar or greater to today's NAND using the ONFI 2.2 standard. The number of maximum write-cycles will also be coming in closer to today's standard than the 3-bit MLC NAND that other companies are pinning their hopes on. Page and block sizes will double on the new chips, to 8KB and 256 pages respectively.

Production of the new multi-level cell chips will start in the second quarter, with mass production ramping up into the third quarter. The first batches will go into embedded products first, while new SSD models getting the new chips are undergoing verification and testing. Intel isn't promising any significant price reductions, but will instead tailor its pricing to meet market demand.

Intel, Micron, and its customers are expected to introduce new SSDs in the latter half of this year using the new technology. Although the company won’t officially confirm any details, Intel is expected to release larger capacities using a newer, faster NAND flash controller.

“To lead the entire semiconductor industry with the most advanced process technology is a phenomenal feat for Intel and Micron, and we look forward to further pushing the scaling limits,” said Brian Shirley, Vice President of Micron’s memory group. “This production technology will enable significant benefits to our customers through higher density media solutions.”

“This will help speed the adoption of solid-state drive solutions for computing,” added Rampone.

IMFT also sees a clear path to NAND flash development below 20nm, despite forecasts of scaling hitting a wall. IMFT is making extensive use of techniques like double mask patterning and immersion lithography, and may end up using EUV lithography in the future.